SN65DSI84TPAPRQ1 Auto Sngl Ch MIPI DSI i SnglLink LVDS
♠ Faʻamatalaga o oloa
| Uiga Oloa | Uiga Taua |
| Tufuga: | Texas Meafaigaluega |
| Vaega o oloa: | LVDS Interface IC |
| Ituaiga: | DSI ile Dual-Link LVDS Bridge |
| Numera o Aveta'avale: | 8 Avetaavale |
| Numera o tagata e mauaina: | 4 Talia |
| Fua Fa'amatalaga: | 1.078 Gb/s |
| Ituaiga Ulufale: | MIPI D-PHY |
| Ituaiga Fa'atino: | LVDS |
| Sapalai Malosi - Max: | 1.95 V |
| Sapalai Voltage - Min: | 1.65 V |
| La'ititi ole Vevela ole Gaioiina: | - 40C |
| Maualuluga Fa'agaioiga Vevela: | + 105 C |
| Tulaga fa'apipi'i: | SMD/SMT |
| Paket/Mata: | HTTP-64 |
| Fa'ailoga: | AEC-Q100 |
| afifiina: | Reel |
| afifiina: | Oti le lipine |
| afifiina: | MouseReel |
| Fa'ailoga: | Texas Meafaigaluega |
| Susū ma'ale'ale: | Ioe |
| Fa'agaoioi Sapalai i le taimi nei: | 106 mA |
| Ituaiga oloa: | LVDS Interface IC |
| Fa'asologa: | SN65DSI84-Q1 |
| Aofaiga o pusa falegaosimea: | 1000 |
| Vaega laiti: | Interface ICs |
| Unit mamafa: | 0.010780 oz |
♠ SN65DSI84-Q1 Automotive Single-Channel MIPI® DSI i le Lua-So'otaga LVDS Bridge
O le alalaupapa SN65DSI84-Q1 DSI-i-LVDS o loʻo faʻaalia ai se faʻaogaina o le MIPI D-PHY pito i luma faʻatasi ma laina e fa i le alalaupapa o loʻo faʻaogaina i le 1 Gbps i le laina ma le maualuga o le bandwidth input o le 4 Gbps. O le alalaupapa e fa'aliliu ai le MIPI® DSI 18-bpp RGB666 ma le 24-bpp RGB888 packets ma fa'aliliuina le fa'asologa o fa'amaumauga vitio i se galuega LVDS o lo'o fa'agaoioia i pika pika o lo'o galue mai le 25 MHz i le 154 MHz, e ofoina atu le LVDS lua po'o le feso'ota'iga tasi LVDS fa'atasi ai ma laina fa'amaumauga e fa i le so'oga.
Ole masini SN65DSI84-Q1 e fetaui lelei mo le WUXGA (1920 × 1080) ile 60 faʻavaa ile sekone (fps) faʻatasi ma le 24 bits-per-pixel (bpp). E fa'atinoina le fa'aputuga o laina fa'apitoa e fa'afetaui ai le fa'aogaina o fa'amaumauga i le va o feso'ota'iga DSI ma le LVDS.
O le masini SN65DSI84-Q1 o loʻo faʻatinoina i se otootoga laʻititi 10 mm × 10 mm HTQFP afifi faʻatasi ma le 0.5-mm pitch, ma faʻaogaina i luga o le vevela mai le -40°C i le 105°C.
1• Agava'a mo Ta'avale Ta'avale
• AEC-Q100 Agavaa ma I'uga nei:
– Vevela o Mea Fa'atonu Vasega 2: –40°C i le 105°C Vevela ole Gaioiina
– Meafaigaluega HBM ESD Fa'avasegaina Laasaga 3A
– Meafaigaluega CDM ESD Fa'avasegaina Laasaga C6
• Fa'atinoina le MIPI D-PHY Version 1.00.00 Layer Fa'aletino Luma-I'uga ma Fa'aali Fa'asologa Fa'asologa (DSI) Version 1.02.00
• Tasi-Tausaga DSI Receiver e mafai ona fa'atulagaina mo le Tasi, Lua, Tolu, po'o le Fa D-PHY Fa'amatalaga Fa'amatalaga i le Alalaupapa Ta'avale e o'o atu ile 1 Gbps ile Lane
• Lagolago 18-bpp ma le 24-bpp DSI Vitio Paketi ma RGB666 ma RGB888 Fa'atulagaina
• E talafeagai mo le 60-fps WUXGA 1920 × 1200 Resolution i le 18-bpp ma le 24-bpp Color, ma le 60-fps 1366 × 768 Resolution i le 18-bpp ma le 24-bpp
• Fa'atonu Fa'atonu mo So'oga Tasi po'o So'oga Lua LVDS
• Lagolagoina le DSI Tasi-Tala i le Faiga Fa'atino LVDS Lua-So'otaga
• LVDS Output-Clock Range o le 25 MHz i le 154 MHz i le Ta'ilua-So'oga po'o So'oga Tasi-Fa'asolo.
• LVDS Pixel Uati e ono maua mai i le FreeRunning Continuous D-PHY Clock po'o le External Reference Clock (REFCLK)
• 1.8 V Autu VCC Malosiaga Tuuina atu
• Fa'ailoga Maualalo Malosi e aofia ai le TOTOGI, Fa'aitiitiga LVDS Output Voltage Swing, Fa'ata masani, ma le MIPI Ultra-Low Power State (ULPS) Lagolago.
• LVDS Channel SWAP, LVDS PIN Order Reverse Feature mo le Faigofie ole PCB Routing
• Fa'aputu i le 64-pin 10 mm × 10 mm HTQFP (PAP) PowerPAD™ IC Package
• Infotainment Head Unit with Integrated Display
• Infotainment Head Unit ma Fa'aaliga Mamao
• Infotainment Rear-Seat Entertainment
• Tu'ufa'atasiga Ta'avale Fa'atosina
• Masini Tautai feavea'i (PND)
• Tautai
• Fefa'ataua'iga o masini a tagata (HMI) ma fa'aaliga
